FinFET devices are integrated into different types of semiconductor devices. FinFET devices typically include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed. A gate is formed over and along the sides of a portion of the semiconductor fins. The increased surface area of the channel and source/drain regions in a FinFET results in faster, more reliable and better-controlled semiconductor transistor devices.
Current FinFET technology, however, has challenges. For example, a slightly larger top fin critical dimension (CD) is desirable to achieve better drive current, but the bottom fin CD needs to remain small to avoid short channel effects (SCE). However, top fin CD and bottom fin CD cannot be controlled independently.
A need therefore exists for methodology enabling fabrication of FinFET devices with a larger top fin CD than a bottom fin CD and the resulting devices.